Citation: Shin, E.; Yoo, C.D. Efficient
Convolutional Neural Networks for
Semiconductor Wafer Bin Map
Classification. Sensors 2023, 23, 1926.
https://doi.org/10.3390/
s23041926
Academic Editors: Kelvin K.L. Wong,
Dhanjoo N. Ghista, Andrew W.H. Ip
and Wenjun (Chris) Zhang
Received: 30 December 2022
Revised: 2 February 2023
Accepted: 3 February 2023
Published: 8 February 2023
Copyright: © 2023 by the authors.
Licensee MDPI, Basel, Switzerland.
This article is an open access article
distributed under the terms and
conditions of the Creative Commons
Attribution (CC BY) license (https://
creativecommons.org/licenses/by/
4.0/).
Article
Efficient Convolutional Neural Networks for Semiconductor
Wafer Bin Map Classification
Eunmi Shin * and Chang D. Yoo *
Korea Advanced Institute of Science and Technology, Daejeon 34141, Republic of Korea
* Correspondence: eunmi.shin@kaist.ac.kr or shinem87@gmail.com (E.S.); cd_yoo@kaist.ac.kr (C.D.Y.);
Tel.: +82-10-3774-1007 (C.D.Y.)
Abstract:
The results obtained in the wafer test process are expressed as a wafer map and contain
important information indicating whether each chip on the wafer is functioning normally. The defect
patterns shown on the wafer map provide information about the process and equipment in which
the defect occurred, but automating pattern classification is difficult to apply to actual manufacturing
sites unless processing speed and resource efficiency are supported. The purpose of this study was to
classify these defect patterns with a small amount of resources and time. To this end, we explored an
efficient convolutional neural network model that can incorporate three properties: (1) state-of-the-art
performances, (2) less resource usage, and (3) faster processing time. In this study, we dealt with
classifying nine types of frequently found defect patterns: center, donut, edge-location, edge-ring,
location, random, scratch, near-full type, and None type using open dataset WM-811K. We compared
classification performance, resource usage, and processing time using EfficientNetV2, ShuffleNetV2,
MobileNetV2 and MobileNetV3, which are the smallest and latest light-weight convolutional neural
network models. As a result, the MobileNetV3-based wafer map pattern classifier uses 7.5 times
fewer parameters than ResNet, and the training speed is 7.2 times and the inference speed is 4.9 times
faster, while the accuracy is 98% and the F1 score is 89.5%, achieving the same level. Therefore, it
can be proved that it can be used as a wafer map classification model without high-performance
hardware in an actual manufacturing system.
Keywords:
wafer map; defect pattern; pattern classification; light-weight convolutional neural networks
1. Introduction
1.1. Background
The semiconductor manufacturing process consists of the front-end process and the
back-end process. In the front-end process, processes such as oxidation, photo, etching,
deposition, and ion implantation are repeatedly performed on the surface of the wafer
to make the wafer into a semiconductor. In the back-end process, a wafer test process
is performed to check whether all processes have been performed properly. Then, the
packaging process of cutting and assembling wafers into chips and final quality inspections
are performed. The wafer test process is important because it provides information to
determine if a problem has occurred in the front-end process and whether each wafer is
operating normally.
Through the wafer test process, the number of normal chips that can be used on one
wafer is counted, and the ratio of the number of normal chips to the total number of chips is
defined as the yield. The yield calculated here is used as a key indicator of semiconductor
productivity, so it is managed with great importance. During the wafer test process, the
defects of each chip are classified into several categories and stored in the form of letters.
In order to check this information at a glance, a wafer bin map is made by distinguishing
defective chips from normal chips and expressing them in different colors. Figure 1 is
an example of a common defect pattern frequently found on wafers. It is a wafer map
Sensors 2023, 23, 1926. https://doi.org/10.3390/s23041926 https://www.mdpi.com/journal/sensors
