Citation: Barzdenas, V.; Vasjanov, A.
A Method of Optimizing
Characteristic Impedance
Compensation Using Cut-Outs in
High-Density PCB Designs. Sensors
2022, 22, 964. https://doi.org/
10.3390/s22030964
Academic Editors: Alvaro
Araujo Pinto and Hacene Fouchal
Received: 22 December 2021
Accepted: 25 January 2022
Published: 26 January 2022
Publisher’s Note: MDPI stays neutral
with regard to jurisdictional claims in
published maps and institutional affil-
iations.
Copyright: © 2022 by the authors.
Licensee MDPI, Basel, Switzerland.
This article is an open access article
distributed under the terms and
conditions of the Creative Commons
Attribution (CC BY) license (https://
creativecommons.org/licenses/by/
4.0/).
Article
A Method of Optimizing Characteristic Impedance
Compensation Using Cut-Outs in High-Density PCB Designs
Vaidotas Barzdenas * and Aleksandr Vasjanov
Department of Computer Science and Communications Technologies, Vilnius Gediminas Technical University,
03227 Vilnius, Lithuania; aleksandr.vasjanov@vilniustech.lt
* Correspondence: vaidotas.barzdenas@vilniustech.lt
Abstract:
The modern era of technology contains a myriad of high-speed standards and proprietary
serial digital protocols, which evolve alongside the microwave and RF realm. The increasing data
rate push the requirements for hardware design, including modern printed circuit boards (PCB). One
of these requirements for modern high-speed PCB interfaces are a homogenous track impedance
all the way from the source to the load. Even though some high-speed interfaces don’t require any
external components embedded into the interconnects, there are others which require either passive
or active components—or both. Usually, component package land-pads are of fixed size, thus, if not
addressed, they create discontinuities and degrade the transmitted signal. To solve this problem,
impedance compensation techniques such as reference plane cut-out are employed for multiple case
studies covering this topic. This paper presents an original method of finding the optimal cut-out size
for the maximum characteristic impedance compensation in high-density multilayer PCB designs,
which has been verified via theoretical estimation, computer simulation, and practical measurement
results. Track-to-discontinuity ratios of 1:1.75, 1:2.5, and 1:5.0 were selected in order to resemble most
practical design scenarios on a 6-layer standard thickness PCB. The measurements and simulations
revealed that the compensated impedance saturation occurs at (150–250%) cut-out widths for a
50 Ω microstrip.
Keywords:
compensation; cut-out; DGS; discontinuity; high-density; high-speed; impedance;
optimization; PCB
1. Introduction
A growing number of high-speed standards and proprietary serial protocols are pos-
ing major design layout challenges for modern printed circuit board (PCB) designers. These
serial standards include Universal Serial Bus [
1
], PCIe Gen1 and PCIe Gen2, Gbps Ether-
net [
2
], LVDS [
3
], Serial RapidIO
®
(SRIO) [
4
], Common Public Radio Interface (CPRI) [
5
],
Double Data Rate (DDR) [
6
], OBSAI, SD/HD/3G/ASI Serial Digital Interface (SDI), XAUI
and Reduced XAUI (RXAUI), HiGig/HiGig+, SATA/Serial Attached SCSI (SAS), GPON,
SerialLite II, Fiber Channel, SONET/SDH, Interlaken, Serial Data Converter (JESD204),
SFI-5, and a host of others [
7
]. All the latter standards link modern high-speed and density
devices either within the realm of a single board (chip-to-chip), in a multi-board design
within a single machine, or in a machine-to-machine (M2M) communication scenario.
While designing chip-to-chip interconnects on a single PCB, high-speed interconnect lines
have strict impedance requirements to meet, which are listed in Table 1.
Sensors 2022, 22, 964. https://doi.org/10.3390/s22030964 https://www.mdpi.com/journal/sensors
